PUBLICATIONS

Conference Proceedings

Calvin Ma, Aditya Mahajan, Brett H. Meyer, “Multi-Armed Bandits for Efficient Lifetime Estimation in MPSoC design,” in the Proceedings of the ACM/IEEE Conference on Design, Automation, and Test in Europe, DATE’17, pp. 1–6, March 2017.

Sean C. Smithson, Guang Yang, Warren J. Gross, and Brett H. Meyer, “Neural networks designing neural networks: Multi-objective hyper-parameter optimization,” in Computer-Aided Design (ICCAD), 2016 IEEE/ACM International Conference on, pp. 1–8, November 2016.

Marco T. Kassis, Yaswanth R. Akaveeti, Brett H. Meyer, and Roni Khazaka, “Parallel transient simulation of power delivery networks using model order reduction,” in the Proceedings of the 25th IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), pp. 1–3, October 2016.

Zaid Al-bayati, Brett H. Meyer, and Haibo Zeng, “Fault-tolerant scheduling of multicore mixed-criticality systems under permanent failures,” in the Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), pp. 1–6, September 2016. (Invited paper)

Mojing Liu and Brett H. Meyer, “Bounding error detection latency in safety critical systems with enhanced execution fingerprinting,” in the Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), pp. 1–6, September 2016.

Dimitrios Stamoulis, Simone Corbetta, Dimitrios Rodopoulos, Pieter Weckx, Peter Debacker, Brett H. Meyer, Ben Kaczer, Praveen Raghavan, Dimitrios Soudris, Francky Catthoor, and Zeljko Zilic, “Capturing true workload dependency of BTI- induced degradation in CPU components,” in the Proceedings of the 26th Edition of the Great Lakes Symposium on VLSI, GLSVLSI ’16, pp. 373–376, May 2016.

Zaid Al-bayati, Jonah Calpan, Brett H. Meyer, Haibo Zeng, “A Four-Mode Model for Efficient Fault-Tolerant Mixed-Criticality Systems,” in the Proceedings of the ACM/IEEE Conference on Design, Automation, and Test in Europe, DATE’16, March 2016.

Seyyed Hasan Mozafari, Brett H. Meyer, “Hot Spare Components for Performance-Cost Improvement in Multi-core SIMT,” in the Proceedings of the 28th IEEE Defect and Fault Tolerance in VLSI and Nanotechnology Systems Symposium, DFT’15, October 2015.

Badrun Nahar, Brett H. Meyer, “RotR: Rotational Redundant Task Mapping for Fail-operational MPSoCs,” in the Proceedings of the 28th IEEE Defect and Fault Tolerance in VLSI and Nanotechnology Systems Symposium, DFT’15, October 2015. (Best Paper Award)

Runjie Zhang, Kaushik Mazumdar, Brett H. Meyer, Ke Wang, Kevin Skadron, Mircea Stan, “Transient Voltage Noise in Charge-Recycled Power Delivery Networks for Many-Layer 3D-IC,” in the Proceedings of the International Symposium on Low Power Electronics Design, ISLPED’15, July 2015.

Vahid Lari, Alexandru Tanase, Jurgen Teich, Michael Witterauf, Faramarz Khosravi, Frank Hannig and Brett H. Meyer, “Co-design Approach for Fault-tolerant Loop Execution on Coarse-grained Reconfigurable Arrays,” in the Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, AHS’15, June 2015. (Invited)

Runjie Zhang, Kaushik Mazumdar, Brett H. Meyer, Ke Wang, Kevin Skadron, Mircea Stan, “A Cross-Layer Design Exploration of Charge-Recycled Power-Delivery in Many-Layer 3D-IC,” in the Proceedings of the Design Automation Conference, DAC’15, June 2015.

Seyyed Hasan Mozafari, Kevin Skadron, Brett H. Meyer, “Yield-aware Performance-Cost Characterization for Multi-Core SIMT,” in the Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI’15, May 2015.

Dimitrios Stamoulis, Dimitrios Rodopoulos, Brett H. Meyer, Dimitrios Soudris, Francky Catthoor, Zeljko Zilic, “Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models,” in the Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI’15, May 2015. (Best Paper Candidate)

Zaid Al-bayati, Youcheng Sun, Haibo Zeng, Marco Di Natale, Qi Zhu, and Brett H. Meyer, “Task Placement and Selection of Data Consistency Mechanisms for Real-Time Multicore Applications,” in the Proceedings of the 21st IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS’15, April 2015.

Dimitrios Stamoulis, Dimitrios Rodopoulos, Brett H. Meyer, Dimitrios Soudris and Zeljko Zilic, “Linear Regression Techniques for Efficient Analysis of Transistor Variability,” in the Proceedings of the 21st IEEE International Conference on Electronics Circuits and Systems, ICECS’14, December 2014.

Runjie Zhang, Ke Wang, Brett H. Meyer, Mircea Stan, Kevin Skadron, “Architecture Implications of Pads as a Scarce Resource,” in the Proceedings of the ACM/IEEE International Symposium on Computer Architecture, ISCA’14, June 2014.

Ke Wang, Brett H. Meyer, Runjie Zhang, Kevin Skadron, Mircea Stan, “Managing C4 Placement for Transient Voltage Noise Minimization,” in the Proceedings of the Design Automation Conference, DAC’14, June 2014.

Saad Arrabi, Liang Wang, David Moore, Ben Calhoun, Kevin Skadron, John Lach and Brett Meyer, “Flexibility and Circuit Overheads in Reconfigurable SIMD/MIMD Systems,” in the Proceedings of the 22nd IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM’14, May 2014. (Poster)

Jiang Chen, Mojing Liu, Brett H. Meyer, “MB-FICA: Multi-bit Fault Injection and Coverage Analysis,” in the Proceedings of the Great Lakes Symposium on VLSI, GLSVLSI’14, May 2014.

Jonah Caplan, Maria Isabel Mera, Peter Milder, Brett H. Meyer, “Trade-offs in Execution Signature Compression for Reliable Processor Systems,” in the Proceedings of the Conference on Design, Automation, and Test in Europe, DATE’14, March 2014.

Ke Wang, Brett H. Meyer, Runjie Zhang, Kevin Skadron, Mircea Stan, “Walking Pads: Fast Power-supply Pad-placement Optimization,” in the Proceedings of the 19th Asia and South Pacific Design Automation Conference, ASP-DAC’14, January 2014. (Best Paper Candidate)

Brett H. Meyer, Mojing Liu, Jonah Caplan, and Georgi Z. Kostadinov, “Rapid, Tunable Error Detection with Execution Fingerprinting,” in the Proceedings of the SAE 2013 AeroTech Congress & Exhibition, September 2013.

Gregory G. Faust, Runjie Zhang, Kevin Skadron, Mircea R. Stan and Brett H. Meyer, “ArchFP: Rapid Prototyping of pre-RTL Floorplans,” in the Proceedings of the IFIP/IEEE International Conference on Large Scale Integration, VLSI-SOC’12, October 2012.

Brett H. Meyer, Benton Calhoun, John Lach, Kevin Skadron, “Cost-effective Safety and Fault Localization using Distributed Temporal Redundancy,” in the Proceedings of the International Conference on Compilers, Architectures and Synthesis of Embedded Systems, CASES’11, October 2011.

Brett H. Meyer, Nishant George, Benton Calhoun, John Lach, Kevin Skadron, “Reducing the Cost of Redundant Execution in Safety-Critical Systems using Relaxed Dedication,” in the Proceedings of the 2011 Conference on Design, Automation, and Test in Europe, DATE’11, March 2011.

Adam S. Hartman, Donald E. Thomas, Brett H. Meyer, “A Case for Lifetime-aware Task Mapping in Embedded Chip Multiprocessors,” in the Proceedings 8th annual conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS’10, October 2010.

Zhenyu Qi, Brett H. Meyer, Wei Huang, Robert Ribando, Kevin Skadron, Mircea Stan, “Temperature to Power Mapping,” in the Proceedings of the 28th IEEE International Conference on Computer Design, ICCD’10, October 2010.

Brett H. Meyer, Adam S. Hartman, Donald E. Thomas, “Slack Allocation for Yield Improvement in NoC-based MPSoCs,” in the Proceedings of the 11th annual International Symposium on Quality Electronic Design, ISQED’10, March 2010.

Brett H. Meyer, Adam S. Hartman, Donald E. Thomas, “Cost-effective Slack Allocation for Lifetime Improvement in NoC-based MPSoCs,” in the Proceedings of the 2010 Conference on Design, Automation, and Test in Europe, DATE’10, March 2010.

Brett H. Meyer, Donald E. Thomas, “Simultaneous Synthesis of Buses, Data Mapping and Memory Allocation for MPSoC,” in the Proceedings of the 5th annual conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS’07, September 2007.

Brett H. Meyer, Donald E. Thomas, “Rethinking Automated Synthesis of MPSoC Architectures,” in the Proceedings of the 21st annual International Parallel and Distributed Processing Symposium, IPDPS’07, March 2007. (invited, NSF Next Generation Software Program)

Journal Articles

Maria Isabel Mera, Jonah Caplan, S. Hasan Mozafari, Brett H. Meyer, Peter Milder, “Area, Throughput and Power Trade-offs for FPGA- and ASIC-based Execution Stream Compression,” ACM Transactions on Embedded Computing Systems (TECS), Special Issue on Secure and Fault-tolerant Embedded Computing, 16(4), May 2017.

S. Hasan Mozafari and Brett H. Meyer, “Efficient performance evaluation of multi-core SIMT processors with hot redundancy,” IEEE Transactions on Emerging Topics in Computing (TETC), July 2016. (In press)

Runjie Zhang, Brett H. Meyer, Ke Wang, Mircea R. Stan, Kevin Skadron, “Tolerating the Consequences of Multiple EM-induced C4 Bump Failures,” IEEE Transactions on VLSI (TVLSI), 24(6), June 2016.

Dimitrios Stamoulis, Kostas Tsoumanis, Dimitrios Rodopoulos, Brett. H. Meyer, Kiamal Pekmestzi, D. Soudris, Z. Zilic, “Efficient Variability Analysis of Arithmetic Units using Linear Regression Techniques,” Analog Integrated Circuits and Signal Processing (ALOG), 87(2), May 2016.

Vahid Lari, Jürgen Teich, Alexandru Tanase, Michael Witterauf, Faramarz Khosravi, Brett H. Meyer, “Techniques for On-Demand Structural Redundancy for Massively Parallel Processor Arrays,” Journal of Systems Architecture (JSA), 61(10), November 2016.

Brett H. Meyer, Adam S. Hartman, Donald E. Thomas, “Cost-effective Lifetime and Yield Optimization for NoC-based MPSoCs,” in ACM Transactions on Design Automation of Electronic Systems (TODAES), 19(2), March 2014.

Lukasz G. Szafaryn, Brett H. Meyer, Kevin Skadron, “Evaluating Overheads of Multibit Soft Error Protection in the Processor Core,” in IEEE Micro, special issue on Reliability Aware Design, July/August 2013.

Karthik Sankaranarayanan, Brett H. Meyer, Wei Huang, Robert J. Ribando, Hossein Haj-Hariri, Mircea R. Stan, Kevin Skadron, “Architectural Implications of Spatial Thermal Filtering,” in Integration, the VLSI Journal, 46(1), January 2012.

Karthik Sankaranarayanan, Brett H. Meyer, Mircea R. Stan, and Kevin Skadron, “Thermal Benefit of Multi-core Floorplanning: A Limits Study,” in Sustainable Computing: Informatics and Systems, 1(4), December 2011.

Brett H. Meyer, Donald E. Thomas, “Rethinking the Synthesis of Buses, Data Mapping, and Memory Allocation for MPSoC,” Design Automation for Embedded Systems, 13(1-2), June 2009. (invited, ESWEEK 2007 special issue)

JoAnn M. Paul, Brett H. Meyer, “Amdahl’s Law Revisited for Single Chip Systems,” International Journal of Parallel Programming, 35(2), April 2007.

Brett H. Meyer, Joshua J. Pieper, JoAnn M. Paul, Jeffery E. Nelson, Sean M. Pieper, Anthony G. Rowe, “Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors,” IEEE Trans. on Computers, 54(6), June 2005.

Workshops and Symposia

Scott D. Dagondon, Warren J. Gross, and Brett H. Meyer, “Sparse-clustered network with selective decoding for internet traffic classification,” in Signal Processing Systems (SiPS), 2016 IEEE Workshop on, pp. 1–6, October 2016.

Sean C. Smithson, Kaushik Boga, Arash Ardakani, Brett H. Meyer, and Warren J. Gross, “SS-stochastic: Stochastic computing can improve upon digital spiking neural networks,” in Signal Processing Systems (SiPS), 2016 IEEE Workshop on, pp. 1–6, October 2016. (Invited paper)

Mojing Liu, Jonah Caplan, Georgi Z. Kostadinov, Brett H. Meyer, “Workload Effects on Execution Fingerprinting for Low-cost Safety-Critical Systems,” Semiconductor Research Corporation TECHCON 2013, September 2013. (Best Paper in Session)

Lukasz G. Szafaryn, Brett H. Meyer, Kevin Skadron, “Evaluating Soft Error Protection Mechanisms in the Context of Multi-bit Errors at the Scope of a Processor,” Semiconductor Research Corporation TECHCON 2012, September 2012.

Daniel A. Epstein, Kevin Skadron, Brett H. Meyer, “Multi-Granularity Redundancy in Multi-Core SIMT,” in the Proceedings of the 6th IEEE Workshop on Design for Manufacturability and Yield, DFM&Y’12, June 2012.

Runjie Zhang, Brett H. Meyer, Wei Huang, Kevin Skadron, Mircea R. Stan, “Some Limits of Power Delivery in Multicore Era,” in the Proceedings of the 4th Workshop on Energy-Efficient Design, WEED’12, June 2012.

Daniel A. Epstein, Kevin Skadron, Brett H. Meyer, “SIMD Performance and Yield Optimization with Multi-granularity Redundancy,” in the Work-in-Progress Session at the 49th IEEE/ACM Design Automation Conference, DAC WIP’12, June 2012.

Marisabel Guevara, Puqing Wu, Mario Donato Marino, Jiayuan Meng, Lukasz G. Szafaryn, Prateeksha Satyamoorthy, Brett H. Meyer, Kevin Skadron, John Lach, Benton Calhoun, “Exploiting Dynamically Changing Parallelism with a Reconfigurable Array of Homogeneous Sub-cores,” Semiconductor Research Corporation TECHCON 2010, September 2010.

Brett H. Meyer, “Cost-effective Lifetime and Yield Optimization for NoC-based MPSoCs,” 13th ACM/SIGDA Ph.D. Forum at DAC, June 2010.

Adam S. Hartman, Brett H. Meyer, Donald E. Thomas, “Lifetime-Aware Task Mapping Using Ant Colony Optimization,” Semiconductor Research Corporation TECHCON 2009, September 2009.

Brett H. Meyer, Adam S. Hartman, Donald E. Thomas, “Architecture and Automation Insights for System-Level Lifetime and Yield Optimization in NoC-based MPSoCs,” 3rd IEEE Workshop on Design for Manufacturability and Yield, DFM&Y’09, July 2009.

Brett H. Meyer, Donald E. Thomas, “Reliability and Cost in NoC-based MPSoCs,” Semiconductor Research Corporation TECHCON 2008, November 2008.

Brett H. Meyer, Donald E. Thomas, “Simultaneous Synthesis of Buses, Data Mapping and Memory Allocation for MPSoC,” Semiconductor Research Corporation TECHCON 2007, September 2007. (best paper in session)

JoAnn M. Paul, Brett H. Meyer, Systems, “Speedup and Heterogeneity,” in the Proceedings of the 3rd Workshop on Application Specific Processors, September 2004.

Book Chapters

JoAnn M. Paul, Brett H. Meyer, “Power-Performance Modeling and Design for Heterogeneous Multiprocessors,” Jörg Henkel, Sri Parameswaran, eds., Designing Embedded Processors: A Low Power Perspective, Springer, Dordrecht, The Netherlands, 2007.

Technical Reports

Greg Faust, Brett H. Meyer, and Kevin Skadron, “Rapid Prototyping of CMP Floorplans: A Technical Report,” Tech. Report CS-2012-02, Univ. of Virginia Dept. of Computer Science, March 2012.

Brett H. Meyer, Adam S. Hartman, Donald E. Thomas, “Execution and Storage Slack Allocation for Lifetime Improvement in NoC-based MPSoCs,” Center for Silicon System Implementation (CSSI) Tech. Report No. 09-01, January 2009.

Brett H. Meyer, “Toward a New Definition of Optimality for Programmable Embedded Systems,” Center for Silicon Systems Implementation (CSSI) Technical Report No. CSSI 05-04, May 2005. (masters thesis)